Welcome to the third issue of the Bartlett Bay Consulting Newsletter. We hope that you find this interesting & informative reading. Please feel free to contact me with any questions or comments. If you wish to "un-subscribe" from future mailings, please use my e-mail link and type "UN-SUBSCRIBE" in the subject line, and your name will be removed from future mailings.

Steve Silverman, President
Bartlett Bay Consulting

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New Clients

Bartlett Bay Consulting has recently been selected to assist in the measurement, analysis, and certification of new products at Rudolph Technologies of Flanders, New Jersey.

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Notes of Interest

Steve Silverman, President of Bartlett Bay Consulting will be leading the ITRS Surface Preparation Focus Team on Backside Particles. This committee is charged with updating the "Backside Particle" section of the 2004 ITRS Roadmap.

If you are interested in being a participant in this committee, please contact Steve (contact information at bottom of newsletter)

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Travel Schedule

Listed below is our travel schedule for near future. If you would like to confirm a date for us to stop by while in your area, please call and we’ll make sure to include a visit to discuss how our services can help your firm. In addition, we would be glad to schedule a special presentation to your staff or other user group interested in learning more about Bartlett Bay Consulting & Contamination Control.

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Q & A

I welcome your feedback & questions! In each issue, I will be answering questions that I receive from you. If you have any questions you wish to submit, please visit www.bartlettbayconsulting.com and use the form provided there.

October's Question:

"Contamination control involves particles in the air as well as on wafers. Is there any direct relationship of the quantity of these particles and the number of defects in the Silicon and failures of the chip?"

A very difficult question, and there is no simple answer. The short (very short!) answer is "Yes". There have been exhaustive studies on these relationships which have led to complicated algorithms which give semiconductor and process engineers an idea of how many particles affect yield.

The entire ITRS roadmap is based on these algorithms. If you are really interested in finding out more about these relationships, I urge you to get involved in an ITRS, SEMI or IEST committee.

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Feature Article:

Measuring Particles on Wafers, Part 3:
Back FOR the future

In our April issue, we explored the problems and intricacies of measuring particles on the frontside (top) of wafers as a criteria for benchmarking contamination levels inside wafer-handling environments (minienvironments, etc). We saw that the specifications on this test were hard to achieve but that a well-designed minienvironment could meet these requirements. In this issue, we look at particles added to the backside (bottom) of the wafers, and you will discover that these adders give an entirely different perspective regarding cleanliness. Furthermore, since the issue of backside particles is so much harder to both understand and measure than frontside particles, this will be a two-part report, with the second part in the next issue.

Before looking closely at the difference between frontside and backside particle adders, we have to address the question of “Why do backside particles matter?”. After all, it is clear that particles on the top of the wafers can directly result in defects on the surface where pattern sensitive lithographic and doping processes occur: it is fairly obvious that a particle on this surface could make a transistor or a chip non-functional. As there are no active devices on the backside (yet!... we may have to visit this issue at some point!), there are two theories as to how particles on the backside could affect the frontside processes:

1) particles on the backside of the wafer could “fall” down onto the wafer(s) beneath. I don’t consider this a viable theory as extensive front side PWP (“Particles per Wafer per Pass”) testing has not shown any evidence of this.

2) particles on the backside could distort the silicon lattice and result in a frontside defect; the size of the offending particles and the actual defect level is not well understood, but it is a valid concern.

If we assume that backside particles are problematic, and most fabs now do, then we have to look at the mechanism of how they get on onto the wafer. Again, a comparison to frontside particle adders is helpful here.

First consider what we know about frontside particle adders: they virtually all result from airborne particles inside the handling areas; there are many sources, but the main thing to remember is that the particles in the environment have to somehow move to the surface of the wafer (which is, for the most part, held horizontally) through the air and then stick to the wafer; however, in a minienvironment which has well designed airflow, the clean air from the filters works to prevent the movement of the particles to the wafer surface. There are many factors in a well-designed minienvironment, but good airflow design is key to keep particle adders low.

Not so for backside particles...

Backside Particle Adders

Backside particle adders are a result of a completely different mechanism:

If we assume that airborne particles won’t land/stick on the backside of wafer (yes, there is the issue of electrostatic attraction, and I will discuss that in the next issue of this newsletter), then all the particles which are found on the backside of the wafer must be due to contact of the handling robot (“Paddles” or “End Effectors”). Simply stated, the more contact times, the more particles.

There-in lies the rub! All this high-tech work which we contamination control experts have devoted to keeping particles off the frontside of wafers through our use of clever methods of airflow handling does little or nothing for the backside, where the cleanliness of the environment plays a secondary role, at best. This is very evident in the particle counts: the PWP specifications for the number frontside particles >0.2um (a good benchmark size for backside particles) in a state of the art minienvironment is in the order of <1 (!); the number of particles added to the backside during a single touch in the minienvironment is in the order of 100s-1000s (!!); it is very evident that these particles are NOT coming from the environment. Unfortunately, we don’t know much more than that!

(Lack of) Knowlege-Base

The list of what we don’t know about the whole issue of backside particles far exceeds what we do know. Much of this is because the problem is a new one, and there have been very few studies to define the techniques/protocols for measurements; take, for example, the fundamental issue of the physics of the transfer mechanism itself: if we knew how the particles are transferred to the wafer, we might have a better idea how to prevent the transfer. The whole issue of backside particles is, in fact in utter confusion by the industry; even the much respected ITRS (International Roadmap for Semiconductors), on which we base literally all of the semiconductor industry specifications, is having problems with the specification. An excerpt from the 2003 update (found in the footnotes for tables 50a and 50b):

“Metrics for critical back surface particle size and back surface particle count are not being listed in 2003. While it is recognized that back surface particles are important to control and are assessed during equipment qualification, there is no clear empirical or theoretical model which links back surface particles to device yield. ... It is not possible to measure absolute levels of back surface particles on in-process wafers due to large variations in back surface finish and films. A generally accepted practice is to process wafers with the polished front surface down in order to assess back surface particle adders for a particular process or operation. Current best practice indicates that back surface particle adders for any particular process step* in 2003 should be less than 400 at 0.2 micron.”

*process step here refers to a single touch by the robot end-effector

Here is what we do know:

When an End Effector touches a wafer, the exact paddle imprint is seen on the wafer (using a wafer scanning tool such as the KLA-Tencor SP1); looking like a fingerprint, particles from the paddle are transferred directly to the backside of the wafer. We know that (surprise, surprise) the fewer contact surfaces the lower the particle counts, and it would appear that the easiest way to meet the an industry spec (if there was one, and at sometime soon, there surely will be as many OEMS and Fabs are coming out with their own) would be to do one of the following:

a. Touch the backside with a minimum contact area or
b. Not touch the backside of the wafer (used edge grip technology) or
c. Find a material that doesn’t transfer the particles or is particle free

Let’s take them in order:

a. Touching the wafer with a minimum contact area is problematic from a point of view of throughput: Whether or not a paddle uses vacuum or the contact surface to hold the wafers during transfer, the paddle must be designed such that it can transport the wafer rapidly between process stations; limiting the contact area rapidly degrades this ability; however, with the right compromise between the right materials and contact are, this solution may work, but as specifications get tighter, it probably is not an workable long-term solution.

b. Edge grip technology is the most viable long term solution to the problem of backside contact/contamination; it, however, hasn’t yet been thoroughly proven, and it has real and potential liabilities, three of which are:

1. Extra width of the end-effector (will not work with certain minienvironment configurations)
2. Possible particle generation (due to holding the thin edge of the wafer)
3. Wafer stresses, etc.

c. Finding material(s) that doesn’t add particles to the backside is the holy grail of the industry, and has the obvious concerns including cost (the biggie!), holding power (the throughput problem), long-term wear/reliability, etc.

If you are still with me, dear reader, then you are probably as confused as everyone else regarding where we are and where we are going in the issue of backside particle problems, specifications, measurements, and protocols.

Next month we will look into how we actually measure the particles, and that will give us some insight as to how we might be able to solve the problem.

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BBC Challenge!

There is no homework problem in this issue (though credit will still be given for submission of answers to the question posed in the April edition), but instead there is a contest. The first person who comes up with the correct answer to the question posed below will receive up to one-hour (one phone call) of Bartlett Bay Consulting time to discuss backside particle issues AT NO CHARGE. A priceless offer.

Here’s the situation: Removing small particles from surfaces has always been problematic, especially for those particles <0.2um (said to be due to van der Waals force)... and yet, engineers have found a method that actually cleans up the robotic End-Effectors.

Yes! Using this method has actually reduced particle counts on these surfaces. The method isn’t perfect, but it has shown to reduce particle counts by about an order of magnitude or more. Impressive!
How? Who knows! (remember the physics of this problem is not at all understood).

Here’s the question:

What is this “high-tech” method”?
(Hint: the answer is buried in the text of this newsletter)

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Sources of Specification Information:

· ITRS - International Technology Roadmap for Semiconductors
· SEMI - Semiconductor Equipment and Materials International
· BBC - Bartlett Bay Consulting. See Contact Information below.

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